User2User | December 10, 2010 | Bangalore, India

Thank you for attending U2U 2010 on December 10th at the Taj Residency.  Presentations are now hosted on the SupportNet site.  Simply click on the link below and login to SupportNet.  If you are a new user please register here.  Once registered, use the link below. 

2010 Bangalore Presentations

Presentations:  Some authors have elected not to publish their presentations due to confidential information.  Those presentations are identified by a (NOT AVAILABLE) following their presentation title & abstract.

KEYNOTE:
Industry Keynote - Walden Rhines, CEO and Chairman, Mentor Graphics (NOT AVAILABLE)
20 Years on the Bleeding Edge - John Cooley, Moderator of Deep Chip (NOT AVAILABLE)
Industry Keynote - Neeraj Paliwal, Vice President and India Country Manager, NXP Semiconductors (NOT AVAILABLE)

SYSTEM DESIGN:
Standard CAD Library Using LP-Wizard - Honeywell (NOT AVAILABLE)
Reality About Virtual Pins  - Nagaraj GC/Vidyashree Urs, GE
Addressing Complex PCB Thermal Issues Using HyperLynx Thermal - Tessolve (NOT AVAILABLE)
Integrity of Power for Better Performance of High-Speed Designs  - S. Lakshminarayanan, HCL Technologies
Best Practices - EMI EMC  - Sumanth.S/Janakiraman.S, GE

FUNCTIONAL VERIFICATION:
Robust, Reusable TLM Testbenches Using MVC's for ARM Bsed SOCs  - Vijayabhaskar Sankaranarayanan, Cypress Semiconductor
"CDC - Clock is Ticking!!" - Intel (NOT AVAILABLE)
Leveraging Digital Centric Mixed-Signal Verification for RF SOC with Questa-ADMS-ADIT - STMicroelectronics (NOT AVAILABLE)
Identification of Power Mode Issues early in the Design Cycle @ RTL  - Srinivas. V, Cypress Semiconductor India
Achieving CDV Using Verification Management Tool - Actel Semiconductor India (NOT AVAILABLE)

DESIGN 2 SILICON:
Handling Complex SoC ECO'S in Ol.ympus  - Sachin Mathur, STMicroelectronics
Achieving Tape-Out in Four Hours from Timing Closure in a 45nm Design  - Amitabh Goyal, Qualcomm
Calibre-InRoute Based Smart LVS in Olympus-SOC - STMicroelectronics (NOT AVAILABLE)
Low Power Methodology for MV-MCMM Using Olympus-SoC - AMD (NOT AVAILABLE)
Filtration of Verification REsults for ORC Recipes  - Rakesh Kuncha, IBM

SILICON TEST:
 A Novel Approach to Improve Test Coverage of BSR Cells - Ankush Srivastava, Freescale Semiconductor
Power Aware ATPG Pattern Generation Technique Using Mentor Low Power edt Flow - STMicroelectornics (NOT AVAILABLE)
Resolution of Test Cube Issue in ATPG Compression Engines  - Anurag Jain, Freescale Semiconductor
Scan Diagnosis Using YieldAssist - Experience and Challenges  - Sarveswara Tammali, Texas Instruments
 

 India Conference Advisory Board (CAB) Members
India U-Innovate Committee Members
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