1. Degree: Bachelor of Engineering
Discipline: Electronics Engineering
Institute: Birla Vishvakarma Mahavidyalaya VV Nagar, Gujarat, India
Year of Passing: September, 1997
2. Degree: Master of Technology
Discipline: Microelectronics and VLSI Systems
Institute: Indian Institute of Technology Kanpur, India
Major subjects: Solid State Devices, Analog and Digital CMOS circuit designs, VLSI systems, VLSI Testing.
Year of Passing: January, 2001
M. Tech. Thesis Title: Modeling and simulation of 2-electrode and 3-electrode AC plasma display panel cell.
1. Company: Amtel India Pvt. Ltd., Baroda, Gujarat
Duration: September-97 to December-98 (1 year and 4 months)
Responsibilities: To develop Microcontroller (MCS-51 series) based Card Access Security systems. My responsibilities were, to develop sensor interfaces, develop
microcontroller based system boards, write assembly level code for the system, and plan test strategy at the system level.
2. Name: Cisco Systems India Pvt. Ltd., Bangalore
Duration: Feb 2001 to September 2004 (3 years and 8 months)
Design and Developments: AC and DC Boundary scan flow, reduced pin count test, IO wrap around test, partition scan design.
Implementation: Scan insertion, Logic BIST, Memory BIST, ATPG, At-speed scan test, TestKompress, scan diagnosis flow, IBM LSSD, RAM sequential ATPG.
Name: Broadcom India Pvt. Ltd., Bangalore
Duration: Oct 2004 to till date (7 years and 1 month)
Design and Developments: AC and DC JTAG flow, Custom Boundary Scan architecture, JTAG based OTP interface design.
Implementation: Logic BIST, Memory BIST, Traditional scan, At-speed scan, JTAG and Boundary scan, Scan compression, Low power scan ATPG, Small delay defects.
- Capture Trigger Scan Architecture (CTSA): CTSA provides generic at-speed scan architecture for LOS based at-speed scan test. CTSA is independent of specific ATPG tool or scan compression technology. Developed CTSA implementation tool sets and signoff flow. Implemented successfully on several Broadcom chips.
- Custom scan structure to test DDR interface at speed: This scan structure was developed to test some components of the DDR interface that cannot be tested by traditional scan ATPG or BIST. These components include dual edge flip flops, delay lines, DDR pads and DDR clocking structure.