Functional Verification Abstracts
Transforming Verification: Revenge of the Respin
10:50am - 11:40pm
Phones are becoming computers. Cars are changing into self-navigating mobile offices. TVs are morphing into 3-D Everything On-Demand Entertainment and Information consoles. Your products are transforming, some even on-the-fly after you deliver them. So why aren't your verification practices transforming as well? This year we will take a focused look at three vital solutions that will not only help you defend the universe against the dreaded Respins (and possibly save your job), but are actually easy to deploy in a matter of days. Leave your manager at the office so you can take all the credit for finding these ways to make you and your verification "more than meets the eye."
Digital to Mixed-Signal Verification of Power Management SOCs using Questa-ADMS
11:40am - 12:20pm
Mathieu Behaghel | ST-Ericsson, Grenoble, France
AMS and RF designs done in ST-Ericsson have big analog functionalities and a lot of interaction between analog and digital functionalities. The partitioning of these designs makes them particularly difficult to verify. The most accurate solution would be to simulate the complete design with a spice simulator, however, increasing time to market constraints and circuit complexity make this approach impossible. As ST-Ericsson is a platform company, models have to be compatible with pure digital tools to simulate all the SOCs platform together. As a consequence, we decided to use a digital centric methodology with real numbers to model the analog functionality. This presentation will show how we developed the models to verify most of the design connectivity and functionality using the speed of digital simulators. It will then describe how Questa-ADMS was used to cover the electrical behavior of the design by reusing the digital on top environment. Examples will be taken from a power management SOC.
Functional safety features in ARM Cortex-R processors
1:40pm - 2:20pm
Christopher B. Turner | ARM Ltd, UK
This presentation will describe the latest ARM Cortex-R high performance embedded processors and introduce their features which relate to functional safety. These features enable the design of microcontroller devices for use in systems requiring high reliability and high availability for integrated control and safety applications. The focus will be on the Cortex-R processor’s capabilities for error detection and correction, deterministic responsiveness and redundancy. Applications for these processors are in automotive and industrial control and these will be discussed together with system design scenarios for arriving at a suitable Automotive Safety Integrity Level (ASIL) in line with the new ISO26262 standard for functional safety.
OVM Adoption: Is it Worth it? Flashback on 4 years of OVM Adoption
2:20pm - 3:00pm
Markus Goertz | ST-Ericsson, Nuremberg, Germany
Adopting new technology is by no doubt a challenge as it requires an up-front investment on the first projects with no guarantee of ROI in the long run if not carefully thought through and planned. 4 years ago, we took the step of moving from? To OVM for our verification IP testbenches. If we take a step back and look behind, we have seen how tools have improved in terms of OVM support, the impact it has on our verification cycle and a first estimation of the ROI. In that session we would like to walk you through our journey and present how we build up our ecosystem, the improvements we have seen in terms of OVM support and the impact of adopting OVM.
Formal Verification of an Interrupt Controller
3:00pm - 3:40pm
Othman Bahlous | Infineon, Munich, Germany
"We describe our efforts to formal verify a real-world interrupt controller design used on an Infineon microcontroller flash memory subsystem. The design under verification does not only have intricate control logic, but it also uses micro-code that is applied as interrupt routines. We use a methodology involving specific steps, including capturing requirements, formulating assertions, and executing a tool. The design behavior is captured by SystemVerilog Assertions (SVA) and run on Questa Formal. Questa Formal was able to catch a logical bug and several design specification ambiguities."