User2User India 2018
Mentor – A Siemens Business User Conference
Vivanta by Taj, MG Road, Bengaluru, May 24, 2018
CALL FOR PAPERS
Are you looking for a platform to present your real world experiences using Mentor Graphics tools to an audience of technical experts who design leading–edge products?
Then submit your abstract for the User2User India and benefit from the conference for your success. User2User India is a one day conference and exhibition dedicated to end-users of Mentor Graphics EDA solutions. Conference keynotes and user presentations address the following domains: IC Design, Verification, Manufacturing and Test, SoC/ASIC /FPGA Design & Verification and Validation/ PCB System Design.
The focus of the conference is ‘Safety & Security’ and is very much technical accommodating the needs of the entire Mentor – A Siemens Business user community in India.
Through “user-presented papers”, delegates will learn of industry best practices together with “tips and tricks” developed whilst using Mentor tools to create leading edge products. The conference is supported by an exhibition of Mentor’s partners and is open all day.
CALL FOR PAPERS IS NOW OPEN:
Submitting an abstract is easy!
Review the technical tracks listed below and determine which track your presentation topic would fit into.
Design 2 Silicon : Track is devoted to the presentation and discussion of all design 2 silicon related topics. The range is quite large and covers both legacy technology nodes which have their technology challenges and advanced technology nodes which require all the latest capabilities and advanced checks.
Silicon Test : Track is devoted to the presentation and discussion of topics related to Design for Test. We will share and discuss usage, experiences and successes with advanced technology nodes and Low Power design.
System Design : Track is devoted to the presentation and discussion of usage, experiences and successes sharing with Mentor System design tools. This includes PCB Placement and Routing tools, Analysis solutions, Data Management, DFM, etc. or the full process.
Functional Verification : Track is devoted to the presentation and discussion of Functional Verification related topics for digital and mixed-signal designs. We will discuss verification methodologies (OVM/UVM) and verification strategies (Low Power (UPF), Formal Verification) addressing the challenges of complex SoC designs and how to extend digital methodologies into AMS designs.
The submission deadline is March 09, 2018. Please email email@example.com with the following information by March 09, 2018:
- First name, Last name, Job title, Company name, company address, Email address, Work phone number
- Topic area – select from the list below
- Presentation title (no more than 10 words)
- Abstract (no more than 150 words)
Gift for every valid abstract/paper submitted before February 28, 2018
All submitted papers will be evaluated with regard to their suitability for the conference by a conference advisory board comprising of Industry Experts and technologists. The author of a submitted paper will be notified of acceptance by April 06, 2018. In case of acceptance, authors need to prepare the final PowerPoint slides by April 30, 2018.
The author agrees that in case of acceptance the title and abstract of his presentation and his name, job title and company name will be published on the conference website and in all print material. The author will also be asked to give his permission to distribute the PowerPoint slides (PDF format) to the conference attendees after the conference.
If you have any further questions, please don’t hesitate to contact us at firstname.lastname@example.org. We are looking forward to your contribution!