View Technical Tracks

Functional Verification

A Proven Methodology for UVM Reuse
Bob Oden | Sales Specialist | Mentor Graphics
10:10am – 11:00am
One of the significant benefits of using a verification methodology like UVM is reuse.  However, reuse is not guaranteed when using UVM.  Reuse requires up-front thought and design when creating transactions, components and environments.  In this presentation we will discuss concepts to consider when creating reusable verification code including the following:  The characteristics of a reusable class.  Horizontal and vertical reuse.  Configuring a class from the outside.  Effective use of SystemVerilog packages and the uvm_config_db.  This presentation will include conceptual discussions as well as working code examples.  The goal of this presentation is to demonstrate reuse on projects within a company site, across company sites and across companies worldwide.

Veloce for FPGA Designs
Nilay Mitash | Sales Specialist | Mentor Graphics
11:10am – 12:00pm

Software and Hardware integration activities in any solution space are becoming extremely critical in getting complex systems into production.  Software activities have traditionally been relegated to post Hardware availability.  However, it is quite evident that, Software is a KEY element that defines the Systems itself, and plays fundamentally in the architectural and implementation of the System.  Hardware functionality tests are not sufficient by themselves and have to be covered with Software interactions as well.  High level of abstraction to implementation is not a segmented activity but a flow-down of process and methods.

Benefits of Early Virtual Verification & System Integration of a Complete System
John Vargas | Sales Specialist | Mentor Graphics
1:00pm – 1:50pm
This session reviews the benefits of early virtual verification and system integration and discusses solutions in that space focusing on SystemVision, a package that integrates with the Capital and Xpedition product suites.  SystemVision provides early virtual verification in the platform level within Capital and at the subsystem and component level within DxDesigner. The presentation includes a case study with of a electromechanical system including software control. Analysis will be performed at the functional and platform level then dive into the details of one sub-system PCB within the DxDesigner environment. Closing the early verification loop of a complete platform-level system and being able to drop into the details of sub-systems as needed provides complete visibility and virtual verification of a complete system.

Static Formal Verification Methods
Dominic Lucido | Application Engineer Consultant | Mentor Graphics
2:00pm – 2:50pm
The purpose of this paper was to explain static formal methods to potential applicants who could benefit from its use.  Formal Verification is one of the most misunderstood areas of DO-254. It is also one of the few actual design or verification methods named in the RTCA/DO-254 document (Appendix B) and is in fact listed as an appropriate method for the “Advanced Verification” requirements for Level A/B designs as well as other safety critical applications.  This presentation will describe the various types of static formal methods, their strength and weakness.  This presentation will show how these methods may help with verification tasks.  It will guide you in choosing the appropriate method to yield a faster and more thorough verification of critical designs.


Layout Design in 3D
Gerald Suiter | Product Marketing Manager | Mentor Graphics
10:10am – 11:00am
Optimizing your PCB design in an electro-mechanical world is a significant challenge. The key is to left-shift mechanical validation into the PCB design process to find electro-mechanical problems earlier, eliminating costly re-design late in the design cycle. Xpedition 3D is a new sub-flow allowing a PCB designer to visualize and edit the PCB in the context of imported mechanical design assemblies within the Xpedition layout environment. The embedded 3D view includes the same selection, planning and placement functionality as Xpedition’s 2D environment. It also includes a complete set of 3D constraints with dynamic collision detection and full batch verification using a true parametric 3D mechanical kernel.  Come and see live demos of this new technology and learn how incorporating 3D into your PCB design process can reduce design time and optimize product quality.

Using Automation to Pinpoint Hard to Find EMI/SI/PI Issues
Jim Cartwright | L3
Ned Dempsher | L3
Ted Lin | Strategic Accounts Application Engineer | Mentor Graphics
Mitra Geeban | Application Engineer Consultant | Mentor Graphics
11:10am – 12:00pm
Manual inspection of PCB artwork is still an essential part of the design signoff in the industry.  However, manual inspection requires a lengthy peer review process which is no guarantee for catching every potential problem. These hard to find issues often are related to EMI/SI/PI as well as other mechanical and manufacturing constraints. Using a solution such as HyperLynx DRC automates the manual inspection of PCB artwork verification.

In this paper we will illustrate how L-3 Communications East in Camden used HyperLynx DRC to locate and examine High Speed digital design issues. HyperLynx DRC found these issues within minutes whereas a lengthy manual inspection process may have missed.

Introducing HyperLynx DRC to your design flow can reduce the overall design and verification cycle time while performing exhaustive checks of the artwork automatically. HyperLynx DRC can be customized to fit many different PCB verification requirements. We find this automated solution vital to our design process.

Mike Orcheski | Senior Application Engineer Consultant | Mentor Graphics
1:00pm – 1:50pm

VX Update for xDX Designer
Mitra Geeban | Application Engineer Consultant | Mentor Graphics
2:00pm – 2:50pm
Continuing the efforts started with EE7.9.4, the VX release includes many enhancements aimed at making xDX Designer more powerful yet easier to use. xDX Designer has been designed with a modern interface that will meet the expectations of both casual and expert users, and by simplifying and automating the interface, your engineers will see an improvement in their efficiency.