Place & Route Abstracts

Implementing a 256 Processor Array Core Using Olympus-SoC
11:00am - 12:00pm
Francois Jacquet | Head of Physical Design | Kalray
Transitioning to 28nm has been a big challenge for designers due to various design complexities. Increasing design sizes, high performance targets, low power needs (advanced Multi-Voltage) and increasing DRC/DFM rule count have a huge impact on project cycle time and quality of results. In this session I will talk about a processor array core netlist to gdsii implementation at 28nm using Olympus-SoC, and how these design challenges were addressed effectively. Advanced Multi-VDD flow including complex PST, Multi Corner, Multi Mode optimization and DRC/DFM sign-off during implementation will also be covered.

Litho-Aware Design Implementation using Calibre LFD and Olympus-SoC
2:00pm - 2:50pm
Fabrice Bernard-Granger, phD | DFM CAD Solution Engineer | STMicroelectronics
Philippe Sardin | DFM Guidelines Engineer | STMicroelectronics
Design For Manufacturing (DFM) is becoming essential to ensure good yield for deep sub-micron technologies. As design rules cannot anticipate all manufacturing marginalities resulting from problematic 2D patterns, the latter has to be addressed at design level through DFM tools.

To deploy DFM strategy on back end levels, STMicroelectronics has implemented a CAD solution for lithographic hotspots search and repair. This allows the detection and the correction, at the routing step, of hotspots derived from lithographic simulation after OPC treatment.

The detection of hotspots is based on Calibre Pattern Match and the repair uses local reroute ability already implemented in Place and Route (PnR) tools. This solution is packaged in a Fast LFD Kit for 28 nm technology and fully integrated in Olympus and other PnR platforms. It offers a solution for multi suppliers CAD vendors routed designs. To ensure a litho friendly repair, the flow integrates a step of local simulation of the rerouted zones using Calibre LFD.

This paper explains the hotspots identification with Calibre LFD, their detection through Calibre Pattern Match, and repair in the Olympus environment thanks to Calibre InRoute. Run time, efficiency rate, timing and RC parasitic impacts are also analyzed.

Improving Productivity & QoR Using Olympus-SoC Automatic Macro Placement (AMP)
3:00pm - 3:50pm
Karthik Sundaram | Hardware Engineer | NVIDIA
With the growth of design sizes, the number of hard macros continues to increase and poses a complex problem for the floorplanning designer. The majority of these macros must be anchored and legalized to the periphery of the design block in order to provide maximum real estate for the regular cell placement. This is a highly iterative and manual process that can have a huge impact on design turn-around time. In this session we will discuss the data path driven Olympus-SoC Auto Macro Placement technology and how it helped converge on a floorplan configuration much faster, and also how it minimized designer intervention. We will cover the different macro placement recipes that were exercised on various blocks and also share some results.

Olympus-SoC - Next Generation Place and Route for 28nm & Below
4:00pm - 4:50pm
Andy Inness | Staff P&R Product Specialist | Mentor Graphics
With the advent of advanced process nodes of 28nm and below, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. They also face multiple design challenges at smaller nodes that impact design performance, power and time to market. Key challenges such as larger design size, stringent low power requirements, multi-mode multi-corner timing, power and SI closure, and lower yield due to manufacturing variations have a major impact on performance and productivity. During this session, we will give an overview of the Olympus-SoC place and route system and how it effectively addresses these challenges, and also give a sneak peek of the product technology roadmap.