User2User | April 12, 2012 | Santa Clara, CA - Presentations available!

Thank you for attending U2U 2012 on April 12th at the Santa Clara Marriott.  This was the 4th year offering our complimentary, one-day user group meeting and it was even more successful.    Presentations are now hosted on the SupportNet site.  Simply click on the link below and login to SupportNet.  If you are a new user please register here.  Once registered, use the link below.

2012 Santa Clara Presentations

Presentations available on SupportNet are listed below:
Some authors have elected not to publish their presentations due to confidential information.  Those presentations are identified by a (NOT AVAILABLE) following their presentation title & abstract.

KEYNOTE:
Doing What Others Don't Do - Walden Rhines, Mentor Graphics
Superphones to Supercomputers:  The Quest for a Trillion Transistor SOC - Sameer Halepete, NVIDIA (NOT AVAILABLE)

CALIBRE:
What You Need to Know to Design at 20nm!  Calibre Roadmap Update - David Abercrombie, Mentor Graphics
Calibre YieldServer to Direct Write OpenAccess Abstracts - Ben Bowers, Qualcomm
Achieving ESD Compliance Using PERC - Jin-Soo Lee, Skyworks Solutions
28nm CMP Sign-Off with Calibre CMPAnalyzer - Goutami Aenuganti, Oracle
Via Redundancy Improvement Using ViaBAR Features in 28nm CMOS Custom - Philippe Sardin, STMicroelectronics

CUSTOM IC/AMS:
Improving AMS Design and Verification Productivity - Ahmed Eisawy, Mentor Graphics
Improinng the Quality of SPICE Simulation Results - Elena Raciti, STMicroelectronics
Mixed Mode Simulation Using Open Access Import to Pyxis - Christopher Arcus, ARasan Chip Systems
Custom IC Design Product Vision and Roadmap - Chris Cone, Mentor Graphics (NOT AVAILABLE)

FUNCTIONAL VERIFICATION:
Transforming Verification:  Revenge of the Respin - Steve Chappell, Mentor Graphics
OVM Testbench API for Accelerating Coverage Closure - Stacey Secatch, XILINX
Verifiying Clock Domain Crossings with Quests Hierarchical CDC Analysis - Shailesh Moolya, Qualcomm
Challenges in Applying a CDC Methodology in a SOC Environment - Mark Kelley, Xilinx
Alternatives to Agent Parameterization - Jeff Kellam, Micron

PCB FLOW:
Best-in-Class Companies Succeed with Best-in-Class Technologies - Joe Krolla, Mentor Graphics (NOT AVAILABLE)
Constraints Driven Design - Rapid Implementation in the DxDesigner/Expedition - Chuck Ohrbom, ViaSat
Transition from BoardStation/BoardArchitect to DxDesigner/Expedition at Autoliv - Joe Borland, Autoliv
How to Put SI Theory to Practical Layout use When Designing High Speed Interfaces - John Medina, High Speed Design

PLACE & ROUTE:
Olympus-SoC - Next Generation Place and Route for 28nm & Below - Andy Inness, Mentor Graphics (NOT AVAILABLE)
Litho-Aware Design Implementation Using Calibre LFD and Olympus-SoC - Fabrice Bernard-Granger, STMicroelectronics
Improving Productivity & QoR Using Olympus-SoC Automatic Macro Placement - Karthik Sundaram, NVIDIA
Implementing a 256 Processor Array Core Using Olympus-SoC - Prashant Varshney, Mentor Graphics (NOT AVAILABLE)

SILICON TEST & YIELD ANALYSIS:
Silicon Test and Yield Analysis Products Update - Gier Eide, Mentor Graphics (NOT AVAILABLE)
Scan Diagnosis with Tessent Diagnosis - Bill Huynh, Marvell
Volume Diagnostic Driven Yield Learning to Improve Manufacturability - Shobhit Malik, GLOBALFOUNDRIES
High-End Test Through TAP - Amer Guettaf, Mentor Graphics (NOT AVAILABLE)