User2User | April 6, 2010 | Santa Clara, CA
Thank you for attending U2U 2010 on April 6th at the Santa Clara Marriott. This was the 2nd year offering our complimentary, one-day user group meeting and it was even more successful. Presentations are nowhosted on the SupportNet site. Simply click on the link below and login to SupportNet. If you are a new user please register here. Once registered, use the link below.
2010 Santa Clara Presentations
Presentations available on SupportNet are listed below:
Some authors have elected not to publish their presentations due to confidential information. Those presentations are identified by a (NOT AVAILABLE) following their presentation title & abstract.
KEYNOTE:
Delivering 10X Design Improvments - Walden Rhines, Mentor Graphics
CALIBRE:
Calibre Product Update & Roadmap - David Abercrombie, Mentor Graphics (NOT AVAILABLE)
Using PERC P2P Resistance Extraction for a Full-Chip Latchup Protection - Sarojini Rajachidambaram, Cypress Semiconductor (NOT AVAILABLE)
Error Waiver Flow and Dangle Metal Check - Bruce Leong & Goutami Aenuganti, Oracle
Identifying Complex Geometric/Electrical Relationships for Latchup Checks - Cory Davis, Cypress Semiconductor
CUCSTOM IC/AMS:
IC Station Roadmap - Tom Daspit, Mentor Graphics (NOT AVAILABLE)
AMS Roadmap - See-Mei Chan, Mentor Graphics (NOT AVAILABLE)
Open Standards for Design Kits from a Customer Perspective - Ron Tinnell, Mentor Graphics
Instance Specific Memory IP Characterization - Federico Politti & Jim McCanny, Altos Design Automation
Predicting Phase-Locked Loop Transistor-Level Phase Noise and Jitter with Eldo RF - Frederic Deboes, Vitesse Semiconductor (NOT AVAILABLE)
FUNCTIONAL VERIFICATION:
No Room for Uni-taskers in My Verification Kitchen - Steve Chappell, Mentor Graphics
Testbench 2.0: Applying Lessons Learned from AVM to an OVM Testbench - Stacy Secath, Xilinx (NOT AVAILABLE)
Accelerated Coverage Closure with inFact in Verification of 802.11 Device - Chandramouli Ganapathy, Atheros Communications (NOT AVAILABLE)
Pain, Possibilities, and Prescriptions: Industry Trends in Advanced Functional Verification - Harry Foster, Mentor Graphics
PCB FLOW:
The Evolution of Mentor PCB Analysis - Steve McKinney, Mentor Graphics (NOT AVAILABLE)
An Exercise in PCB Planning and PCB Process Overview - John Medina, Northrop Grumman
iOrganization: Building High-Performance Engineering Teams for Complex Product Development - Taylor Schull, Mentor Graphics
Chip Planning and Packaging - Vernon Wnek, Broadcom
PLACE & ROUTE:
Mentor Olympus-Soc P&R Update & Roadmap - Arvind Narayanan, Mentor Graphics (NOT AVAILABLE)
Rapid IC Implementation for Low-Power Mobile Devices (Demo) - Jim Schultz, Mentor Graphics (NOT AVAILABLE)
Scalable Computing for Silicon Design - Shesha Krishnapura, Intel (NOT AVAILABLE)
SILICON TEST & YIELD ANALYSIS:
Silicon Test and Yield Analysis Products Update - Stephen Pateras, Mentor Graphics (NOT AVAILABLE)
PLL BIST: A New Paradigm for Embedded Parametric Testing of PLLS - Rakesh Kinger & Swetha Narasimhaswamy, Broadcom (NOT AVAILABLE)
Testing IP Cores Embedded in FPGAs - Ismed Hartanto & Adarsh Pavle, Xilinx (NOT AVAILABLE)
New Challenges in Soc Test - Janusz Rajski, Mentor Graphics (NOT AVAILABLE)