Mr. Rohan Joginpalli has over 11 years of experience in the semiconductors industry, primarily in wireless technologies like WLAN, Bluetooth, Zigbee and WiMax. As Program Manager for the VLSI Department in Redpine Signals, Mr. Joginpalli manages a team of Engineers involved in Verification, Synthesis, DFT, Physical Design, Formal/Physical Verification and Silicon Package, Test/Manufacture and Qualification. Mr. Joginpalli began as a Verification Engineer in the VLSI group of Redpine Signals and transitioned to Design Engineer, Lead Design Engineer, Engineering Manager and Program Manager. He has managed multiple multi-million gate chip tapeouts in 130G and 40LP nodes at different foundries.
Mr. Joginpalli was also a Product Manager in the Systems Business Unit in Redpine and directly managed the company’s Connect-io-n line of products.
Mr. Joginpalli holds a B.Tech. degree in Electronics and Communication Engineering from IIT Guwahati.
Prasanna Kalgikar is Verification Manager at EnSilica India. His past role includes project lead/manager for KPIT Cummins (now Sankalp KPIT) and einfochips. He has a Bachelor of Engineering in Electronics & Communication from Gulbarga University, Karnataka.
He has over 14 years of experience focused on delivering quality IP and SoC level verification services to a global customer base. Previously, he has worked in Consultancy roles in the USA, United Kingdom and Germany. He was an early adaptor of advanced verification methodologies and techniques using Vera-RVM, URM, AVM and formal verification methods and he is now is focused on architecting and creating System Verilog UVM based verification environments.
As a part of his experience, he played key role in creating quality processes for the digital verification teams and integrating with the customers’ requirement.
He has worked in application areas from automotive interfaces such as CAN and MIPI based mobile interfaces for display SOC, camera, and power management devices, audio interfaces, HDMI, etc. He has more recently been working on mixed signal IC verification around UVM-MS and has been leading the development of several VIPs targeted at the connectivity standards for mixed signal ASICs.
Completed Bachelors in ETCE from Jadavpur University in 1997. Joined TI thereafter. Started my career with layout automation before I moved on to leading the standard cell library development and eventually the entire foundation IP portfolio for TI world wide including standard cells, memory compilers, IOs, Efuse. Moved on to the role of platform manager for an internal Flash node development within TI. Career spanning over 15.5 years in TI. Then founded Immensa Semiconductors in 2013 continuing the passion of digital foundation IP development along with co founders Dharin Shah and Girishankar Gurumurthy , ex colleagues in TI.
Suresh is a highly accomplished design and verification expert with over 22 years of experience in the VLSI industry and has led several complex core, chip and SoC projects. Previously, Suresh worked at IBM as Program Director, building the Processor front-end development team that was responsible for the design and verification of complex IBM processors like Z-series, Power series and PowerPC cores used in mainframes, servers and embedded applications.
Prior to IBM, Suresh had a long career at Texas Instruments as General Manager for the Wireless Solutions Group (Digital) and prior to that, General Manager for the digital SoC development at Broadband Systems Technology Center. He has the experience of leading more than 10 SoC tape-outs, building strong technical teams and managing big teams of 100+ engineers.
Suersh holds an M.Tech degree in Integrated Circuits and Systems from IIT Madras.
Dr. Sankara Reddy earned his Ph.D in faculty of engineering, Indian Institute of Science, Bangalore in 1997 and M.Tech from Indian Institute of Technology Kharagpur in 1984. He has 26 years of experience in microelectronics and VLSI area. He has built teams from scratch, managed and grew the circuit design team in the areas of std cell, IO, SOC designs (RTL to GDSII), high speed transceiver and IP development of analog and digital cores. Prior to Co-founding a full fledged analog/interface IP design company, Terminus Circuits Pvt Ltd, He held senior level management position at IBM where he has built, led and managed design groups. He also had contributed at senior level positions. Prior to this he was at IISc Institute of Science (www.iisc.ernet.in) as faculty member in ECE department for 15 years and was responsible for research and development in the advanced areas of microelectronics.
Dr. Reddy holds 6 patents (published/filed) and has 15 published papers in refereed journals and technical conferences.