User2User | June 9, 2009 | Santa Clara, CA 

Thank you for attending U2U 2009 on June 9th at the Santa Clara Marriott.  This was the first complimentary, one-day user group meeting and it was a success.   Presentations are now available below for download, please click on the link below.

Agenda: [ print version ]  

• Calibre Track: [ print version ]
• Custom IC/AMS Track: [ print version ]
• Functional Verification Track:  [ print version ] 
• Silicon Test & Yield Analysis (formerly DFT) Track:  [ print version ] 

Presentations:  Some authors have elected not to publish their presentations due to confidential information. 

Calibre Track:

• Calibre nmLVS/xRCPMM Roadmap  - Carey Robertson, Mentor Graphics (NOT AVAILABLE)
• Getting the Most of Smart Fill by Solving Density Requirements  - Norma Rodriguez, AMD 
• Advanced Physical Verification at 40nm:  Calibre Best Practices  - Kuldeep Singh, Sun Microsystems
• Ease of LVS Debugging with the New Improved Calibre RVE - Padma Musunuri, Micron
• "Yes we can" shrink the die size, but how?  Todd Lukanc, Spansion

Silicon Test & Yield Analysis Track:

• Silicon Test and Yield Analysis Update - Bruce Swanson, Mentor Graphics (NOT AVAILABLE)
• Test Pattern Generation Methods for Small Delay Defect Testing - Narendra Devta-Prasana, LSI  (NOT AVAILABLE)
• Hierarchical DFT Implementation in Industrial Design – Case Study - Saket Kumar Goyal, LSI (NOT AVAILABLE)
• Low Pin Count Test with Embedded Compression  - Srinivas Komar, Mentor Graphics
• Pushing the Envelope with TestKompress - Haluk Konuk, Broadcom (NOT AVAILABLE)

Functional Verification Track:

• What Do You Need to Improve your Verification Throughput  - Chuck Seeley, Mentor Graphics
• Time-to-Market Design Quality with Open Verification Methods (OVM) - Mark Glasser, Mentor Graphics
• Accelerating Coverage Closure  - Steve Chappell, Mentor Graphics
• Clock-Domain-Crossings:  Coverage Confidence in the face of Metastability - Dr. Ping Yeung, Mentor Graphics

Custom IC/AMS Track: